The present invention relates generally to disk controllers and more particularly to disk controllers having a multiported memory architecture.
Conventional computer systems typically include several functional units. These functional units may include a central processing unit (CPU), main memory, input/output devices, and magnetic disk drives. In conventional systems, the main memory is tightly coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU quick access to data or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system including the combination of the CPU and the main memory is often referred to as a host system.
The main memory is typically smaller than the magnetic disk drive. The main memory is usually volatile, while the magnetic disk drive is non-volatile. Therefore, programming data information is often stored on the magnetic disk drive and is read into the main memory as needed. In contrast to the main memory, which is closely coupled to the CPU, the magnetic disk drive is usually more remotely coupled to the CPU. Because the magnetic disk drive is more remotely coupled to the CPU, access to the magnetic disk drive is typically slower and more complicated than access to the main memory. A disk controller typically couples the host system to the magnetic disk drive and handles the complex details of interfacing the magnetic disk drive to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces.
The magnetic hard disk drive assembly usually consists of one or more magnetic disks. Each disk typically has a number of concentric rings or tracks on which data is stored. The tracks themselves are further divided into sectors which are the smallest accessible data unit. A sector is accessed by positioning a magnetic head above the appropriate track. The first sector of a track is typically identified by an index pulse. The start of each other track sector is identified with a sector pulse. The drive waits until the desired sector rotates beneath the head and then proceeds to read or write the data. The date is accessed serially, one bit at a time. Usually, each disk in the disk drive has its own read/write head.
The disk drive is connected to the disk controller. The disk controller performs numerous functions, such as, for example, converting digital data to analog head signals, converting analog head signals to digital data, disk formatting, error checking, logical-to-physical address mapping, and data buffering. For example, the disk drive typically formats the data from the drive. The data from the drive is serially arranged and the disk controller converts the serial data into a parallel arrangement.
The data buffering function is used in transferring data between the host and the mass storage memory. Data buffering is needed because the speed at which the disk drive can supply or accept data from the host is different then the speed at which the host can correspondingly read or supply the data. Therefore, the disk controller conventionally contains a buffer memory that temporarily stores data being read or written to the hard drive to synchronize the data with the speed of the I/O bus to which it is connected. Thus, the buffer decouples the rate at which data is exchanged between the drive and host and the rate at which data is written and read from the drive. The buffering function is particularly necessary because each sector is read or written as a whole.
In addition to providing access to both the I/O bus and the disk drive, the buffer memory often is accessed by a local processor on the disk controller. Thus, the disk controller buffer memory may be accessed by many functional portions of the disk controller and by the host. In conventional systems, the competition for access to the buffer memory is often a bottleneck which greatly restricts the data transfer rates between the buffer memory and the functional units, as well as to the disk drive and the host.
Another performance bottleneck found in conventional disk controllers is the local processor. The local processor typically manages an I/O bus interface circuit, the buffer memory, the disk formatter, as well as management of the disk controller as a whole. Furthermore, conventional systems require the local processor to manage data transfers through the buffer memory at a low level. Typical general-purpose processors are inadequate to handle such application specific functions in an efficient manner.
In addition, conventional disk controllers do not fully utilize their processors. For example, if, while transferring data from the disk to the I/O bus using one or more the disk controller processors, the transfer outpaces the disk""s ability to supply data, the processors are wastefully paused until the disk catches up.
The present invention is generally related to efficient and flexible methods and systems of buffering and accessing data being written to or read from mass storage devices.
In one embodiment, a disk controller includes a data buffer used to buffer data transferred between a mass storage device and an I/O bus. In another embodiment, the data buffer includes a multi-port memory. The multi-port memory is coupled to a plurality of channels, such as, by way of example, a disk channel and an I/O channel, as well as one or more processors.
In one embodiment, the multi-port memory may be used as both a random access memory and a first-in-first-out (FIFO) memory. Thus, when used as a first-in-first out memory, the multi-port memory may be used to buffer data between the disk channel and I/O channel. The multi-port memory may be used for context switching, wherein register data from one or more processors is swapped in or out of the memory. The efficient register swapping provided by one embodiment of the present invention advantageously allows the processor to quickly switch between tasks. This is very useful if a first task is in a wait state, because rather than wasting processor time pausing while waiting for the wait state to end, the processor can quickly switch to another task, and then, after the wait state has ended for the first task, switch back to the first task.
In addition, in one embodiment, the random access feature allows selected data stored in the multi-port memory to be swiftly retrieved. For example, if the memory is used to store a Fibre Channel frame and associated CRC data, the CRC data can be immediately retrieved without having to read out the entire frame.
In one embodiment, the multi-port memory is a DMA (direct memory access) memory. In an exemplary embodiment, the multi-port memory""s ports include a random access port, a FIFO access port, a register access port, and/or a buffer controller DMA port. The random access port is connected to a microprocessor interface bus which in turn is connected to one or more processors, such as a microprocessor and a microcontroller, as well as the FIFO access port. The register access port is may also be connected to one or processors, such as a microcontroller. The buffer controller DMA port is connected to a CRC (cyclic redundancy code) checker and to a buffer memory.
In one embodiment, the multi-port memory contains 64 bytes and can hold an entire Fibre Channel protocol command. Furthermore, a state machine associated with the multi-port memory can perform several commands. In another embodiment, one or more of the commands are configured to efficiently manage I/O packets or frames. In yet another embodiment, the state machine commands include one or more of the following: a fetch current FCP (Fibre Channel Protocol) command, an update current FCP pointer command, a load FIFO command, an unload FIFO command, a load FIFO with CRC, an unload FIFO with CRC, a write to buffer memory command, and a read from buffer memory command. In one embodiment, a command is provided that causes the transfer of an entire Fibre Channel command into the FIFO without further intervention from the microprocessor or the microcontroller. One embodiment provides direct frame access to Fibre Channel frames. In another embodiment, the commands may be halted and/or paused.